The present invention relates to voltage generating circuits, and, more particularly, to a method and circuit for regulating a charge pump circuit to minimize the ripple and the power consumption of the charge pump circuit.
In many electronic circuits, charge pump circuits are utilized to generate a positive pumped voltage having an amplitude greater than that of a positive supply voltage, or to generate a negative pumped voltage from the positive supply voltage, as understood by those skilled in the art. For example, in a conventional dynamic random access memory (xe2x80x9cDRAMxe2x80x9d), a charge pump circuit may be utilized to generate a boosted word line voltage VCCP having an amplitude greater than the amplitude of a positive supply voltage VCC,and a negative voltage pump circuit may be utilized to generate a negative substrate or back-bias voltage Vbb that is applied to the bodies of NMOS transistors in the DRAM. Another typical application of a charge pump circuit is the generation of a high voltage utilized to erase data stored in blocks of memory cells or to program data into memory cells in non-volatile electrically block-erasable or xe2x80x9cFLASHxe2x80x9d memories, as will be understood by those skilled in the art.
FIG. 1 is a schematic of a conventional two-stage charge pump circuit 100 that generates a pumped output voltage VP having an amplitude greater than the amplitude of a supply voltage source VCC in response to complementary clock signals CLK and {overscore (CLK)}, as will be described in more detail below. The charge pump circuit 100 includes two voltage-boosting stages 102 and 104 connected in series between an input voltage node 106 and an output voltage node 108. The voltage-boosting stage 102 includes a capacitor 110 receiving the clock signal CLK on a first terminal and having a second terminal coupled to the input node 106. A diode-coupled transistor 112 is coupled between the input voltage node 106 and a voltage node 114, and operates as a unidirectional switch to transfer charge stored on the capacitor 110 to a capacitor 116 in the second voltage-boosting stage 104. The capacitor 116 is clocked by the complementary clock signal {overscore (CLK)}. A transistor 118 transfers charge stored on the capacitor 116 to a load capacitor CL when the transistor 118 is activated. A threshold voltage cancellation circuit 122 generates a boosted gate signal VBG responsive to the CLK and {overscore (CLK)} signals, and applies the signal VBG to control activation of the transistor 118. When the CLK and {overscore (CLK)} signals are high and low, respectively, the circuit 122 drives the signal VBG low to turn OFF the transistor 118, and when the CLK and {overscore (CLK)} signals are low and high, respectively, the circuit 122 drives the signal VBG high to turn ON the transistor 118. The cancellation circuit 122 may be formed from conventional circuitry that is understood by those skilled in the art. The charge pump circuit 100 further includes a diode-coupled transistor 120 coupled between the supply voltage source VCC and node 106. The diode-coupled transistor 120 operates as a unidirectional switch to transfer charge from the supply voltage source VCC to the capacitor 110.
A ring oscillator 124 generates an oscillator clock signal OCLK that is applied to a switching circuit 126 coupled between the ring oscillator 124 and a clocking-latching circuit 128. The switching circuit 126 receives a regulation output signal REGOUT from external control circuitry (not shown in FIG. 1), and when the REGOUT signal is inactive low, the switching circuit 126 presents a low impedance and thereby applies the OCLK signal to the clocking-latching circuit 128. When the REGOUT signal is active high, the switching circuit 126 presents a high impedance, which isolates or removes the OCLK signal from the clocking-latching circuit 128. The clocking-latching circuit 128 latches the applied OCLK signal and generates the complementary clock signals CLK and {overscore (CLK)} responsive to the latched OCLK signal. The CLK and {overscore (CLK)} signals have the same frequency as the OCLK signal, and are complementary signals so there is a phase shift of 180xc2x0 between these signals.
The operation of the conventional charge pump circuit 100 will now be described in more detail with reference to the timing diagram of FIG. 2, which illustrates the voltages at various points in the charge pump circuit 100 during operation. In operation, the charge pump circuit 100 operates in two modes, a normal mode and a power-savings mode. During both the normal and power-savings modes of operation, the ring oscillator 124 continuously generates the OCLK signal. The charge pump circuit 100 operates in the normal mode when the pumped output voltage VP is less than a desired pumped output voltage VPD. When VP less than VPD, the external control circuitry drives the REGOUT signal inactive low causing the switching circuit 126 to apply the OCLK signal to the clocking-latching circuit 128. In response to the applied OCLK signal, the clocking-latching circuit 128 latches the OCLK and clocks the stages 102 and 104 with the CLK and {overscore (CLK)} signals generated in response to the latched OCLK signal.
At just before a time t0, the CLK signal is low having a voltage of approximately 0 volts and the {overscore (CLK)} signal is high having a voltage of approximately the supply voltage VCC, and each of the voltages on the nodes 106, 114, and 108 and the have assumed values as shown for the sake of example. Also, before the time t0 the REGOUT signal is inactive low and the circuit 122 drives the boosted gate signal VBG high responsive to the CLK and {overscore (CLK)} signals being low and high, respectively. When the CLK signal is low, the terminal of the capacitor 110 is accordingly at approximately ground and the voltage at the node 106 is sufficiently low to turn ON the diode-coupled transistor 120, transferring charge from the supply voltage source VCC through the transistor 120 to charge the capacitor 110. As shown in FIG. 2, the voltage at the node 106 (i.e., the voltage across the capacitor 110) is increasing just before the time t0 as the capacitor 10 is being charged. Also just before the time t0, the voltage at the node 114 equals the high voltage of the {overscore (CLK)} signal plus the voltage stored across the capacitor 116 (V116). This bootstrapped voltage on the node 114 is sufficiently greater than the voltage VP on the output voltage node 108 to turn ON the transistor 118, transferring charge from the capacitor 116 through the transistor 118 to the load capacitor CL. As shown, the voltage at node 114 is decreasing and the voltage VP increasing just before the time t0 as charge is being transferred through the transistor 118.
At the time t0, the CLK signal goes high, driving the voltage on the node 106 to the high voltage (VCC) of the CLK signal plus the voltage stored across the capacitor 110 (V110). At this point, the voltage on the node 106 is sufficiently high to turn OFF the transistor 120, isolating the node 106 from the supply voltage source VCC. Also at the time t0, the {overscore (CLK)} signal goes low (to ground), causing the voltage on the node 114 to equal the voltage V116 stored across the capacitor 116. The voltage on the node 106 is now sufficiently greater than the voltage on the node 114 to turn ON the transistor 112, transferring charge from the capacitor 110 through the transistor 112 to the capacitor 116. As shown in FIG. 2, between the time t0 and a time t1, which corresponds to the interval the CLK signal is high and {overscore (CLK)} signal is low, the voltage at the node 106 decreases and the voltage at the node 114 increases as charge is pumped or transferred through the transistor 112. It should be noted that during this time, the transistor 118 is turned OFF because the voltage VP is sufficiently greater than the voltage at the node 114 during normal operation of the charge pump circuit 100.
At the time t1, the CLK and {overscore (CLK)} signals go low and high, respectively, and the charge pump circuit 100 operates in the same manner as previously described for just before the time t0. In other words, the transistor 112 turns OFF and transistors 118 and 120 turn ON, and charge is transferred from the supply voltage source VCC through the transistor 120 to the capacitor 110 and charge is transferred from the capacitor 116 through the transistor 118 to the load capacitor CL. As seen in FIG. 2, from the time t1 to a time t2 the voltage at the node 106 increases as the capacitor 110 is charging and the voltages on nodes 114 and 108 decrease and increase, respectively, as charge is transferred from the capacitor 116 to the load capacitor CL. At the time t2, the CLK and {overscore (CLK)} signals again go high and low, respectively, and the charge pump circuit 100 operates as previously described at the time t0.
The charge pump circuit 100 continues operating in this manner during the normal mode, pumping charge from the supply voltage source VCC to the successive capacitors 110, 116, and CL to develop the desired pumped voltage VPD across the capacitor CL. When the pumped output voltage VP becomes greater than the desired voltage VPD, the charge pump circuit 100 commences operation in the power-savings mode of operation, which occurs at a time t3 in FIG. 2. In response to the pumped output voltage VP becoming greater than the desired voltage VPD, the external control circuit drives the REGOUT signal active high, causing the switching circuit 126 to present a high impedance so that the OCLK signal no longer clocks the clocking-latching circuit 128 which, in turn, no longer clocks the voltage-boosting stages 102 and 104. As a result, the CLK and {overscore (CLK)} signals remain in their previous latched states until the pumped output voltage VP is less than VPD. This is seen in the example of FIG. 2 at a time t4 when, although the OCLK signal goes high, the CLK and {overscore (CLK)} signals remain low and high, respectively, since OCLK signal is not applied to the clocking-latching circuit 128.
Once the pumped output voltage VP becomes less than VPD, the control circuit drives the REGOUT signal inactive low and the charge pump circuit 100 again commences operation in the normal mode. As will be understood by those skilled in the art, the switching circuit 126 enables the charge pump circuit 100 to very quickly switch into the normal mode of operation since the ring oscillator 124 continually generates the OCLK signal. In other words, since the ring oscillator 124 continuously generates the OCLK signal, transition from the power-savings to normal mode is delayed only by the switching time of the circuit 126, which is very fast. In contrast, if the ring oscillator 124 was turned ON and OFF responsive to the REGOUT signal, the settling time (i.e., the time for the CLK, {overscore (CLK)} signals to stabilize) of the oscillator when turned back ON is much greater than the switching time of the circuit 126. As a result, in this situation the voltage VP could continue to decrease during this settling time, thereby increasing the ripple of the voltage VP.
The power-savings mode of operation reduces the overall power consumption of the circuit 100 since the CLK and {overscore (CLK)} signals do not clock the stages 102 and 104 when the voltage VP is greater than the desired voltage VPD. Although the overall power consumption of the circuit 100 is reduced and the switching circuit 126 alleviates some of the ripple introduced by switching between modes, operation in the power-savings mode introduces additional ripple of the pumped output voltage VP due to the transistor 118 in the final voltage-boosting stage 104 remaining turned ON during this mode of operation. More specifically, when the charge pump circuit 100 enters the power savings mode of operation the CLK and {overscore (CLK)} signals have one of two states. If the CLK and {overscore (CLK)} signals are high and low, respectively, when the REGOUT signal goes active to enter the power-savings mode, then the boosted gate signal VBG remains low during this mode and the transistor 118 is turned OFF. In this situation, the turned OFF transistor 118 isolates the output node 108 and the voltage VP is not affected by the voltage on the node 114.
In contrast, if the CLK and {overscore (CLK)} signals are low and high, respectively, when the REGOUT signal goes active, the transistor 118 may remain turned ON during the power-savings mode thereby coupling the output node 108 to the node 114. As a result, the voltage on the node 114 affects the pumped output voltage VP in this situation. For example, as illustrated in FIG. 2, it is seen that when the REGOUT signal goes high at the time t3 the CLK and {overscore (CLK)} signals are low and high, respectively, so the signal VBG is high turning ON the transistor 118. As seen after the time t3, the pumped output voltage VP continues to increase as charge is transferred from the capacitor 116 through the transistor 118 to the load capacitor CL. Thus, the pumped voltage VP undesirably increases after time t3 even though it is already greater than the desired voltage VPD, thereby increasing the ripple of the pumped output voltage.
There is a need for a charge pump circuit having a low power consumption and a reduced ripple of the generated pumped output voltage.
According to one aspect of the present invention, a charge pump circuit includes a plurality of charge pump stages coupled in series, each including an input terminal, an output terminal, a clock terminal, a capacitor, and a switch. The capacitor of each charge pump stage is coupled between the clock terminal and the input terminal, and the switch of each charge pump stage is coupled between the input terminal and the output terminal. The input terminal of a first charge pump stage in the series is coupled to a voltage source and the output terminal of a last charge pump stage in the series is coupled to a pumped voltage output terminal. The switches of all charge pump stages but the last charge pump stage are selectively closed to allow current to flow in a first direction and selectively opened to prevent current flow in a second direction that is opposite the first direction. The switch of the last charge pump stage has a control input that is coupled to a control terminal. A clocking circuit applies first and second complementary digital signals to the clock terminals of the respective charge pump stages with the charge pump stages that receive the first digital signal alternating with the charge pump stages that receive the second digital signal. A control circuit applies a control signal to the control terminal to allow current to flow in the first direction when the absolute value of a pumped voltage at the pumped voltage output terminal has a magnitude that is less than a predetermined value and to prevent current from flowing in the first direction when the absolute value of the pumped voltage at the pumped voltage output terminal has a magnitude that is greater than the predetermined value.